Dynamic table sharing of memory space within a network device

ABSTRACT

A network device for processing data on a data network includes a port interface configured to receive a data packet from a data network and to send a processed data packet to an egress port of the plurality of ports, a packet evaluation module configured to parse the received data packet and modify the received data packet to form the processed data packet and a search engine configured to perform searches of lookup tables using parsed data packet values and to return search results to the packet evaluation module to assist in modifying the received data packet. At least one lookup table shares at least two different types of entries in that same at least one lookup table, where the search engine is configured to distinguish between the at least two different types of entries in that same at least one lookup table.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. Utilityapplication Ser. No. 11/084,482, filed on Mar. 21, 2005, which claimspriority of U.S. Provisional Patent Application Ser. No. 60/653,943,filed on Feb. 18, 2005. The subject matter of this earlier filedapplications are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a network device for processing data ina network and more particularly to use of memory in a network devicethat allows for static and dynamic sharing of tables.

2. Description of the Related Art

A network may include one or more network devices, such as Ethernetswitches, each of which includes several modules that are used toprocess information that is transmitted through the device.Specifically, the device may include port interface modules, designed tosend and receive data over a network, a Memory Management Unit (MMU), tostore that data until it is forwarded or further processed andresolution modules, that allow the data to be reviewed and processedaccording to instructions. The resolution modules include switchingfunctionalities for determining to which destination port data should bedirected. One of the ports on the network device may be a CPU port thatenables the device to send and receive information to and from externalswitching/routing control entities or CPUs.

Many network devices operate as Ethernet switches, where packets enterthe device from multiple ports, where switching and other processing areperformed on the packets. Thereafter, the packets are transmitted to oneor more destination ports through the MMU. The process of determining anegress port for a packet involves examining the packet to determineattributes.

Part of the process of determining the packet attributes includessearching of table entries in memory to determine quantities to directand modify the packet. For example, an IP destination address may bederived from the packet header, that may not, without table lookups,determine an egress port of the network device that the packet should besent from to reach that destination IP address. Such a decision processrequires a lookup in the memory tables. However, memory available to thedevice is finite and requirements for tables and table sizes may not beknown definitively until the network device is put into service. Thus,there is a need for a network device that allows for more flexible usageof tables in memory to comport with different network trafficsituations.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention thattogether with the description serve to explain the principles of theinvention, wherein:

FIG. 1 illustrates a network device in which an embodiment of thepresent invention may be implemented;

FIG. 2 illustrates a block diagram illustrating the communication usingports of the network device of FIG. 1 according to an embodiment of theinstant invention;

FIGS. 3A-3B illustrate memory structures to be used with the networkdevice of FIG. 1, with FIG. 3A illustrating the shared memory that isexternal to the network device and FIG. 3B illustrating the Cell BufferPool of the shared memory architecture;

FIG. 4 illustrates buffer management mechanisms that are used by thememory management unit to impose resource allocation limitations andthereby ensure fair access to resource;

FIG. 5 illustrates a two stage parser, according to certain embodimentsof the present invention;

FIG. 6 illustrates another parser for use with interconnected port,according to certain embodiments of the present invention;

FIG. 7 illustrates a result matcher, according to certain embodiments ofthe present invention;

FIG. 8 illustrates a configuration of an egress port arbitrationimplemented in the present invention; and

FIGS. 9A-9C illustrate sharing of tables, according to severalembodiments of the present invention, with FIG. 9A illustrating statictable separation, FIG. 9B illustrating dynamically updated tables andFIG. 9C illustrating table separation based on a key format.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference will now be made to the preferred embodiments of the presentinvention, examples of which are illustrated in the accompanyingdrawings.

FIG. 1 illustrates a network device, such as a switching chip, in whichan embodiment the present invention may be implemented. Device 100includes ingress/egress modules 112 and 113, a MMU 115, a parser 130 anda search engine 120. Ingress/egress modules are used for buffering ofdata and forwarding the data to the parser. The parser 130 parses thedata received and performs look ups based on the parsed data using thesearch engine 120. The primary function of MMU 115 is to efficientlymanage cell buffering and packet pointer resources in a predictablemanner, even under severe congestion scenarios. Through these modules,packet modification can occur and the packet can be transmitted to anappropriate destination port.

According to several embodiments, the device 100 may also include oneinternal fabric high speed port, for example a HiGig™ port or high speedport, 108, one or more external Ethernet ports 109 a-109 x, and a CPUport 110. High speed port 108 is used to interconnect various networkdevices in a system and thus form an internal switching fabric fortransporting packets between external source ports and one or moreexternal destination ports. As such, high speed port 108 may notexternally visible outside of a system that includes the multipleinterconnected network devices. CPU port 110 is used to send and receiveinformation to and from external switching/routing control entities orCPUs. According to an embodiment of the invention, CPU port 110 may beconsidered as one of external Ethernet ports 109 a-109 x. Device 100interfaces with external/off-chip CPUs through a CPU processing module111, such as a CMIC, which interfaces with a PCI bus that connectsdevice 100 to an external CPU.

In addition, the search engine module 120 may be composed of additionalsearch engine modules, 122, 124 and 126, that are used to performparticular look ups that are used in the characterization andmodification of data being processed by the network device 100.Likewise, the parser 130 also includes additional modules that aredirected to parsing data received from the internal fabric high speedport 134 and the other ports 138, with other modules 132 and 136 forforwarding data back to the ports of the network device. The high speedport 134 and the two stage 138 parsers are discussed in greater detailbelow.

Network traffic enters and exits device 100 through external Ethernetports 109 a-109 x. Specifically, traffic in device 100 is routed from anexternal Ethernet source port to one or more unique destination Ethernetports. In one embodiment of the invention, device 100 supports twelvephysical Ethernet ports 109, each of which can operate in 10/100/1000Mbps speed and one high speed port 108 which operates in either 10 Gbpsor 12 Gbps speed.

The structure of the physical ports 109 are further illustrated in FIG.2. A series of serializing/deserializing modules 103 send and receivedata, where data received as each port is managed by a port manager102A-L. The series of port managers have a timing generator 104 and abus agent 105 that facilitate their operation. The data received andtransmitted to a port information base so that the flow can bemonitored. It is noted that high speed port 108 has similarfunctionalities but does not require as many elements since only oneport is being managed.

In an embodiment of the invention, device 100 is built around a sharedmemory architecture, as shown in FIGS. 3A-3B wherein MMU 115 enablessharing of a packet buffer among different ports while providing forresource guarantees for every ingress port, egress port and class ofservice queue associated with each egress port. FIG. 3A illustrates theshared memory architecture of the present invention. Specifically, thememory resources of device 100 include a Cell Buffer Pool (CBP) memory302 and a Transaction Queue (XQ) memory 304. CBP memory 302 is anoff-chip resource that is made of, according to some embodiments, 4 DRAMchips 306 a-306 d. According to an embodiment of the invention, eachDRAM chip has a capacity of 288 Mbits, wherein the total capacity of CBPmemory 302 is 122 Mbytes of raw storage. As shown in FIG. 3B, CBP memory302 is divided into 256K 576-byte cells 308 a-308 x, each of whichincludes a 32 byte header buffer 310, up to 512 bytes for packet data312 and 32 bytes of reserved space 314. As such, each incoming packetconsumes at least one full 576 byte cell 308 (e.g., byte cells 308 a-308x). Therefore in an example where an incoming packet includes a 64 byteframe, the incoming packet will have 576 bytes reserved for it eventhough only 64 bytes of the 576 bytes is used by the frame.

Returning to FIG. 3A, XQ memory 304 includes a list of packet pointers316 a-316 x into CBP memory 302, wherein different XQ pointers 316 maybe associated with each port. A cell count of CBP memory 302 and apacket count of XQ memory 304 is tracked on an ingress port, egress portand class of service basis. As such, device 100 can provide resourceguarantees on a cell and/or packet basis.

Once a packet enters device 100 on a source port 109, the packet istransmitted to parser 130 for processing. During processing, packets oneach of the ingress and egress ports share system resources 302 and 304.In specific embodiments, two separate 64 byte bursts of packets areforwarded to the MMU from the local ports and the high speed port. FIG.4 illustrates buffer management mechanisms that are used by MMU 115 toimpose resource allocation limitations and thereby ensure fair access toresources. MMU 115 includes an ingress backpressure mechanism 404, ahead of line mechanism 406 and a weighted random early detectionmechanism 408. The ingress backpressure mechanism 404 supports losslessbehaviour and manages buffer resources fairly across ingress ports. Headof line mechanism 406 supports access to buffering resources whileoptimizing throughput in the system. Weighted random early detectionmechanism 408 improves overall network throughput.

The ingress backpressure mechanism 404 uses packet or cell counters totrack the number of packets or cells used on an ingress port basis. Theingress backpressure mechanism 404 includes registers for a set of 8individually configurable thresholds and registers used to specify whichof the 8 thresholds are to be used for every ingress port in the system.The set of thresholds include a limit threshold 412, a discard limitthreshold 414 and a reset limit threshold 416. If a counter associatedwith the ingress port packet/cell usage rises above discard limitthreshold 414, packets at the ingress port will be dropped. Based on thecounters for tracking the number of cells/packets, a pause flow controlis used to stop traffic from arriving on an ingress port that have usedmore than its fair share of buffering resources, thereby stoppingtraffic from an offending ingress port and relieving congestion causedby the offending ingress port.

Specifically, each ingress port keeps track of whether or not it is inan ingress backpressure state based on ingress backpressure countersrelative to the set of thresholds. When the ingress port is in ingressbackpressure state, pause flow control frames with a timer value of(0xFFFF) are periodically sent out of that ingress port. When theingress port is no longer in the ingress backpressure state, the pauseflow control frame with a timer value of 0x00 is sent out of the ingressport and traffic is allowed to flow again. If an ingress port is notcurrently in an ingress backpressure state and the packet counter risesabove limit threshold 412, the status for the ingress port transitionsinto the ingress backpressure state. If the ingress port is in theingress backpressure state and the packet counter falls below resetlimit threshold 416, the status for the port will transition out of thebackpressure state.

The head of line mechanism 406 is provided to support fair access tobuffering resources while optimizing throughput in the system. The headof line mechanism 406 relies on packet dropping to manage bufferingresources and improve the overall system throughput. According to anembodiment of the invention, the head of line mechanism 406 uses egresscounters and predefined thresholds to track buffer usage on a egressport and class of service basis and thereafter makes decisions to dropany newly arriving packets on the ingress ports destined to a particularoversubscribed egress port/class of service queue. Head of linemechanism 406 supports different thresholds depending on the color ofthe newly arriving packet. Packets may be colored based on metering andmarking operations that take place in the ingress module and the MMUacts on these packets differently depending on the color of the packet.

According to an embodiment of the invention, head of line mechanism 406is configurable and operates independently on every class of servicequeue and across all ports, including the CPU port. Head of linemechanism 406 uses counters that track XQ memory 304 and CBP memory 302usage and thresholds that are designed to support a static allocation ofCBP memory buffers 302 and dynamic allocation of the available XQ memorybuffers 304. A discard threshold 422 is defined for all cells in CBPmemory 302, regardless of color marking. When the cell counterassociated with a port reaches discard threshold 422, the port istransition to a head of line status. Thereafter, the port may transitionout of the head of line status if its cell counter falls below a resetlimit threshold 424.

For the XQ memory 304, a guaranteed fixed allocation of XQ buffers foreach class of service queue is defined by a XQ entry value 430 a-430 h.Each of XQ entry value 430 a-430 h defines how many buffer entriesshould be reserved for an associated queue. For example, if 100 bytes ofXQ memory are assigned to a port, the first four class of service queuesassociated with XQ entries 430 a-430 d respectively may be assigned thevalue of 10 bytes and the last four queues associated with XQ entries430 d-430 h respectively may be assigned the value of 5 bytes.

According to an embodiment of the invention, even if a queue does notuse up all of the buffer entries reserved for it according to theassociated XQ entry value, the head of line mechanism 406 may not assignthe unused buffer to another queue. Nevertheless, the remainingunassigned 40 bytes of XQ buffers for the port may be shared among allof the class of service queues associated with the port. Limits on howmuch of the shared pool of the XQ buffer may be consumed by a particularclass of service queue is set with a XQ set limit threshold 432. Assuch, set limit threshold 432 may be used to define the maximum numberof buffers that can be used by one queue and to prevent one queue fromusing all of the available XQ buffers. To ensure that the sum of XQentry values 430 a-430 h do not add up to more than the total number ofavailable XQ buffers for the port and to ensure that each class ofservice queue has access to its quota of XQ buffers as assigned by itsentry value 430, the available pool of XQ buffer for each port istracked using a port dynamic count register 434, wherein the dynamiccount register 434 keeps track of the number of available shared XQbuffers for the port. The initial value of dynamic count register 434 isthe total number of XQ buffers associated with the port minus a sum ofthe number of XQ entry values 430 a-430 h. Dynamic count register 434 isdecremented when a class of service queue uses an available XQ bufferafter the class of service queue has exceeded its quota as assigned byits XQ entry value 430. Conversely, dynamic count register 434 isincremented when a class of service queue releases a XQ buffer after theclass of service queue has exceeded its quota as assigned by its XQentry value 430.

When a queue requests XQ buffer 304, head of line mechanism 406determines if all entries used by the queue is less than the XQ entryvalue 430 for the queue and grants the buffer request if the usedentries are less then the XQ entry value 430. If however, the usedentries are greater than the XQ entry value 430 for the queue, head ofline mechanism 406 determines if the amount requested is less than thetotal available buffer or less then the maximum amount set for the queueby the associated set limit threshold 432. Set limit threshold 432 is inessence a discard threshold that is associated with the queue,regardless of the color marking of the packet. As such, when the packetcount associated with the packet reaches set limit threshold 432, thequeue/port enters into a head of line status. When head of linemechanism 406 detects a head of line condition, it sends an updatestatus so that packets can be dropped on the congested port.

However, due to latency, there may be packets in transition between theMMU 115 and the ports and when the status update is sent by head of linemechanism 306. In this case, the packet drops may occur at MMU 115 dueto the head of line status. In an embodiment of the invention, due tothe pipelining of packets, the dynamic pool of XQ pointers is reduced bya predefined amount. As such, when the number of available XQ pointersis equal to or less than the predefined amount, the port is transitionto the head of line status and an update status is sent to by MMU 115 tothe ports, thereby reducing the number of packets that may be dropped byMMU 115. To transition out of the head of line status, the XQ packetcount for the queue must fall below a reset limit threshold 436.

It is possible for the XQ counter for a particular class of servicequeue to not reach set limit threshold 432 and still have its packetdropped if the XQ resources for the port are oversubscribed by the otherclass of service queues. In an embodiment of the invention, intermediatediscard thresholds 438 and 439 may also be defined for packetscontaining specific color markings, wherein each intermediate discardthreshold defines when packets of a particular color should be dropped.For example, intermediate discard threshold 438 may be used to definewhen packets that are colored yellow should be dropped and intermediatediscard threshold 439 may be used to define when packets that arecolored red should be dropped. According to an embodiment of theinvention, packets may be colored one of green, yellow or red dependingon the priority level assigned to the packet. To ensure that packetsassociated with each color are processed in proportion to the colorassignment in each queue, one embodiment of the present inventionincludes a virtual maximum threshold 440. Virtual maximum threshold 440is equal to the number of unassigned and available buffers divided bythe sum of the number of queues and the number of currently usedbuffers. Virtual maximum threshold 440 ensures that the packetsassociated with each color are processed in a relative proportion.Therefore, if the number of available unassigned buffers is less thanthe set limit threshold 432 for a particular queue and the queuerequests access to all of the available unassigned buffers, head of linemechanism 406 calculates the virtual maximum threshold 440 for the queueand processes a proportional amount of packets associated with eachcolor relative to the defined ratios for each color.

To conserve register space, the XQ thresholds may be expressed in acompressed form, wherein each unit represents a group of XQ entries. Thegroup size is dependent upon the number of XQ buffers that areassociated with a particular egress port/class of service queue.

Weighted random early detection mechanism 408 is a queue managementmechanism that preemptively drops packets based on a probabilisticalgorithm before XQ buffers 304 are exhausted. Weighted random earlydetection mechanism 408 is therefore used to optimize the overallnetwork throughput. Weighted random early detection mechanism 408includes an averaging statistic that is used to track each queue lengthand drop packets based on a drop profile defined for the queue. The dropprofile defines a drop probability given a specific average queue size.According to an embodiment of the invention, weighted random earlydetection mechanism 408 may defined separate profiles on based on aclass of service queue and packet.

As illustrated in FIG. 1, the MMU 115 receives packet data for storagefrom the parser 130. As discussed above, the parser 130 includes a twostage parser, where that portion is illustrated schematically in FIG. 5.The data are received at ports 501 of the network device, as discussedabove. Data may also be received through the CMIC 502, where that datais passed to an ingress CMIC interface 503. The interface acts toconvert the CMIC data from a P-bus format to an ingress data format. Inone embodiment, the data is converted from 45-bit to 168-bit format,such that the latter format includes 128-bit data, 16-bit control andpossibly a 24-bit high speed header. The data are thereafter sent in64-bit bursts to the ingress arbiter 504.

The ingress arbiter 504 receives data from the ports 501 and the ingressCMIC interface 503, and multiplexes those inputs based on time divisionmultiplexing arbitration. Thereafter, the data are sent to the MMU 510,where any high speed header is removed and the format is set to a MMUinterface format. Packet attributes are checked, such as end-to-end,Interrupted Bernoulli Process (IBP) or Head of Line (HOL) packets. Inaddition, the first 128 bytes of data are snooped and the high speedheader is passed to the parser ASM 525. If the burst of data receivedcontains an end marker, the CRC result is sent to the result matcher515. Also, the packet length is estimated from the burst length and a126-bit packet ID is generated for debugging purposes.

The parser ASM 525 converts the 64 data burst, at 4 cycles per burst,into 128-byte burst, at 8 cycles per burst. The 128-byte burst data isforwarded to both the tunnel parser 530 and the parser FIFO 528 at thesame time to maintain the same packet order. The tunnel parser 530determines whether any type of tunnel encapsulation, including MPLS andIP tunnelling, is being employed. In addition, the tunnel parser alsochecks for outer and inner tags. Through the parsing process, thesession initiated protocol (SIP) is provided for subnet based VLAN,where the SIP parsing occurs if the packet is an address resolutionprotocol (ARP), reverse ARP (RARP) or IP packet. A trunk port grid ID isalso constructed based on the source trunk map table, unless there is notrunking or if the trunk ID is obtained from the high speed header.

The tunnel parser 530 works with the tunnel checker 531. The tunnelchecker checks the checksum of the IP header, and characteristics of UDPtunnelling and IPv6 over IPv4 packets. The tunnel parser 530 utilizesthe search engine 520 to determine the tunnel type through preconfiguredtables.

The parser FIFO 528 stores 128 bytes of packet headers and 12 bytes ofhigh speed headers that is parsed again by the deep parser 540. Theheader bytes are stored while the search engine completes a search andis ready for the deeper search. Other attributes are also maintained bythe FIFO, such as packet length, high speed header status and the packetID. The deep parser 540 provides three different types of data,including search results from the search engine 520 that are “flowthrough,” inner parser results and high speed module header. Specialpacket types are determined and passed along to the search engine. Thedeep parser 540 reads the data from the parser FIFO, where pre-definedfields are parsed. The search engine provides lookup results based onthe values passed to the search engine, where the packet ID is checkedto maintain packet order.

The deep parser 540 also uses the protocol checker 541 to check theinner IP header checksum, check for denial of service attack attributes,errors in the high speed module header and perform a martian check. Thedeep parser also works with the field processor parser 542, to parsepredefined fields and user defined fields. The predefined fields arereceived from the deep parser. These fields include MAC destinationaddress, MAC source address, inner and outer tags, Ether type, IPdestination and source addresses, Type of Service, IPP, IP flags, TDS,TSS, TTL, TCP flags and flow labels. User defined fields are alsoparsible, up to 128-bit lengths.

As discussed above, the data that is received on the high speed port istreated separately from other data received on the local ports. Asillustrated in FIG. 1, high speed port 108 has its own buffers and dataflows from the port to its own parser 134. The high speed parser isillustrated in greater detail than FIG. 6. The structure is similar tothe two stage parser, illustrated in FIG. 5, with several differences.Data received at the high speed port 601 is forwarded to the high speedport assembler 604. The assembler receives the data and high speedheader in 64 byte bursts, with a similar format as used for the localports. The data are sent to the MMU 610 without the high speed headerand in a MMU interface format.

The first 128 bytes of the data is snooped and sent, along with the highspeed header, to the deep parser 640. With similarity to the two stageparser, end-to-end message are checked, with the parsed results beingsent in a side band. Also similarly, the CRC and packet lengths arechecked by the result matcher 615. In addition, a 16 bit packet ID isgenerated for use in debugging and tracking the flow of the packet.

The high speed version of the deep parser 640 is a subset of the twostage deep parser 540, and performs similar functions. There is,however, no pass through of information from the search engine 620, itcannot skip the MPLS header and parse the payload only and does not senddeep data to the search engine. In function, the high speed version ofthe FP parser 642 is the same as the FP parser 542 discussed above.

The result matcher is illustrated in greater detail in FIG. 7. It isnoted that the result matcher may be used commonly between the parsersor each parser may utilize its own result matcher. In the embodimentillustrated, both types of ports 710 & 720 receive data and forwardquantities to the result checker through the actions of the ingressassembler 715 and the ingress arbiter 725. The quantities include portnumber, presence of EOF, the CRC and the packet length. The resultmatcher acts as a series of FIFOs to match search results through theuse of the search engine 705. The tag and the Management InformationBase (MIB) event are matched with the packet length and the CRC statuson a per port basis. The MIB event, CRC and port are also reported tothe Ingress MIB 707. The search results are provided every 4 cycles forboth network ports and high speed port. The structure allows for resultsto be stored in the result matcher per port if there is a delay that islonger than the incoming packet time and awaiting the end of packetresults when the search delay is shorter than the incoming packet time.

After the process of parsing and evaluating of data received, aforwarding decision is made with regard to the received information. Theforwarding decision is generally made as to what destination port thepacket data should be sent to, although the decision can be made to dropa packet or forward a packet to a CPU or other controller through theCMIC 111. On egress, the packet is modified based on the parsing andevaluation of the network device. Such modification can include tagging,modification of header information or addition of a module header, ifthe egress port is the high speed port. The modification is performed ona cell basis to avoid delays in the forwarding of the packet data.

FIG. 8 illustrates a configuration of an egress port arbitrationimplemented in the present invention. According to FIG. 8, MMU 115 alsoincludes a scheduler 802 that provides arbitration across the eightclass of service queues 804 a-804 h associated with each egress port toprovide minimum and maximum bandwidth guarantees. It is noted that whileeight classes of service are discussed, other formulations of classes ofservice are also supported. Scheduler 802 is integrated with a set ofminimum and maximum metering mechanisms 806 a-806 h that each monitorstraffic flows on a class of service basis and an overall egress portbasis. Metering mechanisms 806 a-806 h support traffic shaping functionsand guarantee minimum bandwidth specifications on a class of servicequeue and/or egress port basis, wherein scheduling decisions by schedule802 are configured largely via traffic shaping mechanisms 806 a-406 halong with a set of control masks that modify how scheduler 802 usestraffic shaping mechanisms 806 a-806 h.

As shown in FIG. 8, minimum and maximum metering mechanisms 806 a-806 hmonitor traffic flows on a class of service queue basis and an overallegress port basis. Maximum and minimum bandwidth meters 806 a-806 h areused to feed state information to scheduler 802 which responds bymodifying its service order across class of service queues 804. Thenetwork device 100 therefore enables system vendors to implement aquality of service model by configuring class of service queues 804 tosupport an explicit minimum and maximum bandwidth guarantee. In anembodiment of the invention, metering mechanisms 806 a-806 h monitortraffic flow on a class of service queue basis, provides stateinformation regarding whether or nor a class of service flow is above orbelow a specified minimum and maximum bandwidth specification, andtransmits the information into scheduler 802 which uses the meteringinformation to modify its scheduling decisions. As such, meteringmechanisms 806 a-806 h aid in partitioning class of service queues 804into a set of queues that have not met the minimum bandwidthspecification, a set that have met its minimum bandwidth but not itsmaximum bandwidth specification and a set that have exceeded its maximumbandwidth specification. If a queue is in the set that have not met itsminimum bandwidth specification and there are packets in the queue,scheduler 802 services the queue according to the configured schedulingdiscipline. If a queue is in the set that have met its minimum bandwidthspecification but has not exceeded it maximum bandwidth specificationand there are packets in the queue, scheduler 802 services the queueaccording to the configured scheduling discipline. If a queue is in theset that have exceeded its maximum bandwidth specification or if thequeue is empty, scheduler 802 does not service the queue.

The minimum and maximum bandwidth metering mechanisms 806 a-806 h may beimplemented using a simple leaky bucket mechanism which tracks whetheror not a class of service queue 804 has consumed its minimum or maximumbandwidth. The range of the minimum and maximum bandwidth setting foreach class of service 804 is between 64 kbps to 16 Gbps, in 64 kbpsincrements. The leaky bucket mechanism has a configurable number oftokens “leaking” out of buckets, each of which is associated with one ofqueues 804 a-804 h, at a configurable rate. In metering the minimumbandwidth for a class of service queue 804, as packets enter the classof service queue 804, a number of tokens in proportion to the size ofthe packet is added to a respective bucket, having a ceiling of buckethigh threshold. The leaky bucket mechanism includes a refresh updateinterface and a minimum bandwidth which defines how many tokens are tobe removed every refresh time unit. A minimum threshold is set toindicate whether a flow has satisfied at least its minimum rate and afill threshold is set to indicate how many tokens are in leaky bucket.When the fill threshold rises above minimum threshold, a flag whichindicates that the flow has satisfied its minimum bandwidthspecification is set to true. When fill threshold falls below minimumthreshold, the flag is set to false.

After metering mechanisms 806 a-806 h indicate that the maximumbandwidth specified has been exceeded high threshold, the scheduler 802ceases to service the queue and the queue is classified as being in theset of queues that have exceeded it maximum bandwidth specification. Aflag is then set to indicate that the queue has exceeded its maximumbandwidth. Thereafter, the queue will only receive service fromscheduler 802 when its fill threshold falls below high threshold and theflag indicating that it has exceeded its maximum bandwidth is reset.

Maximum rate metering mechanism 808 is used to indicate that the maximumbandwidth specified for a port has been exceeded and operates in thesame manner as meter mechanisms 806 a-806 h when the maximum totalbandwidth has been exceeded. According to an embodiment of theinvention, the maximum metering mechanism on a queue and port basisgenerally affects whether or not queue 804 or a port is to be includedin scheduling arbitration. As such, the maximum metering mechanism onlyhas a traffic limiting effect on scheduler 802.

On the other hand, minimum metering on a class of service queue 804basis has a more complex interaction with scheduler 802. In oneembodiment of the invention, scheduler 802 is configured to support avariety of scheduling disciplines that mimic the bandwidth sharingcapabilities of a weighted fair queuing scheme. The weighted fair queuescheme is a weighted version of packet based fair queuing scheme, whichis defined as a method for providing “bit-based round robin” schedulingof packets. As such, packets are scheduled for access to an egress portbased on their delivery time, which is computed as if the scheduler iscapable of providing bit-based round robin service. A relative weightfield influences the specifics of how the scheduler makes use of theminimum metering mechanism, wherein the scheduler attempts to provide aminimum bandwidth guarantee.

In one embodiment of the invention, the minimum bandwidth guarantee is arelative bandwidth guarantee wherein a relative field determines whetheror not scheduler 802 will treat the minimum bandwidth metering settingsas a specification for a relative or an absolute bandwidth guarantee. Ifthe relative field is set, the scheduler treats minimum bandwidth 806setting as a relative bandwidth specification. Scheduler 802 thenattempts to provide relative bandwidth sharing across backlogged queues804.

As discussed above, the present invention allows for more flexible useand configuration of lookup tables in memory. It should be noted thatfor particular embodiments discussed above, where lookup tables are setup in memory external to the network device, the concept of tablesharing may be important in allowing more tables to be kept in smallermemory areas. Three memory sharing process are discussed below, wherethose processes may be used separately or together.

The first table sharing process involves the setting of static blockboundaries, as illustrated in FIG. 9A. The memory space is broken intoblocks that can be designated as Table A, Table B, etc. The assignmentof blocks is statically configured by software and the network devicedoes not change the configuration. A table 901-a may be configured intoa first table containing L2 entries and a second table containing L3entries. Alternatively, the same table 901-b may be configured throughdifferent blocks, to tables having L2, L3v4 and L3v6 entries. Thus thesoftware at start up has the option of partitioning the blocks as neededfor the environment in which the network device is being used. In aparticular embodiment, the table is separated into four blocks.

Another table sharing process involves more use of the hardware of thenetwork device to control the table sharing. As illustrated in FIG. 9B,the table entries of the table 902 are inserted in two directions. Thememory space is broken into blocks, for example eight blocks, that canbe designated as Table A or Table B. Table A grows top down, while TableB grows bottom up. When the hardware is instructed to insert an entryinto Table A for the first time, it designates block 0 as Table A. Whenthe hardware is instructed to insert an entry into Table B for the firsttime, it designates, for example, block 7 as Table B. When a blockbecomes full, a new block is assigned to dynamically grow the tableeither up or down. When the two tables meet, i.e. there are no furtherblocks left to grow, the tables are full. In other words, the table canbe constructed on the fly by the network device to respond to itsprocessing needs.

A third table sharing process involves the separation of a table basedon key format. The table type is encoded into the key itself, so thatthere is an entry by entry sharing of the memory space. FIG. 9Cillustrates the process. In the embodiment illustrated, no blocks areneeded, but the key is used to determine whether a particular table isused. The key and result entries are in table 905. The key is 64 bits,in one embodiment, and certain bits that are not used can be used toidentify the type of entry. Thus, for example if bits [63:56]=FF, thatmay detail that the entry is an IPv6 entry, whereas other bit values mayindicate that it is an IPv4 entry.

The above-discussed processes of table sharing of memory space allow forextremely configurable switching by the network device. Static tableboundaries, as discussed in the first method, allow a customer to moldthe tables into a configuration that is customized for their particularenvironment. Table separation based on the key, as discussed in thethird method, and table separation based on dynamically updated blockboundaries, as discussed in the above second method, allow the networkdevice to dynamically grow and/or shrink tables based on how thecustomer uses and populates the tables.

The foregoing description has been directed to specific embodiments ofthis invention. It will be apparent, however, that other variations andmodifications may be made to the described embodiments, with theattainment of some or all of their advantages. Therefore, it is theobject of the appended claims to cover all such variations andmodifications as come within the true spirit and scope of the invention.

What is claimed is:
 1. A network device comprising: a tunnel parserconfigured to determine whether tunneling is being employed by checkingat least one received packet for inner and outer tags; a tunnel typedeterminer configured to determine a tunnel type being employed by theat least one received packet based on a first set of one or more valuesincluded in the at least one received packet; and a port determinerconfigured to determine at least one egress port via which to send theat least one received packet based on a second set of one or more valuesincluded in the at least one received packet.
 2. The network device ofclaim 1, further comprising a port interface configured to receive theat least one received packet from a data network and to send the atleast one received packet to one or more egress ports.
 3. The networkdevice of claim 2, further comprising the one or more egress ports. 4.The network device of claim 1, further comprising a parser configured toparse fields of the at least one received data packet.
 5. The networkdevice of claim 1, further comprising a parser FIFO configured tomaintain a length(s) of the at least one received data packet.
 6. Thenetwork device of claim 5, further comprising a packet evaluation moduleconfigured to forward the at least one received data packet to both thetunnel parser and the parser FIFO to maintain a same packet order. 7.The network device of claim 1, further comprising: a lookup tableincluding: entries of a first type for determining an egress port viawhich to send received data packets of a first type; and entries of asecond type for determining an egress port via which to send receiveddata packets of a second type; wherein the port determiner is configuredto determine the at least one egress port by checking the lookup table.8. The network device of claim 1, further comprising at least oneingress backpressure counter configured to determine whether the networkdevice is in a backpressure state.
 9. The network device of claim 8,wherein the network device is configured to send at least one pausecontrol frame based on the at least one ingress backpressure counterdetermining that the network device is in the backpressure state. 10.The network device of claim 1, wherein the tunnel type determiner isconfigured to determine the tunnel type by checking the first set of oneor more values against at least one preconfigured table.
 11. A methodperformed by a network device, the method comprising: determiningwhether tunneling is being employed by checking at least one receivedpacket for inner and outer tags; determining a tunnel type beingemployed by the at least one received packet based on a first set of oneor more values included in the at least one received packet; anddetermining at least one egress port via which to send the at least onereceived packet based on a second set of one or more values included inthe at least one received packet.
 12. The method of claim 11, furthercomprising receiving the at least one received packet from a datanetwork.
 13. The method of claim 12, further comprising sending the atlast one packet via one or more egress ports.
 14. The method of claim11, further comprising parsing fields of the at least one received datapacket.
 15. The method of claim 11, further comprising maintaining alength(s) of the at least one received data packet.
 16. The method ofclaim 15, further comprising forwarding the at least one received datapacket to both a tunnel parser and a parser FIFO to maintain a samepacket order.
 17. The method of claim 11, further comprising determiningat least one egress port by checking a lookup table.
 18. The method ofclaim 11, further comprising determining whether the network device isin a backpressure state.
 19. The method of claim 18, further comprisingsending at least one pause control frame based on the determining thatthe network device is in the backpressure state.
 20. A network devicecomprising: means for determining whether tunneling is being employed bychecking at least one received packet for inner and outer tags; meansfor determining a tunnel type being employed by the at least onereceived packet based on a first set of one or more values included inthe at least one received packet; and means for determining at least oneegress port via which to send the at least one received packet based ona second set of one or more values included in the at least one receivedpacket.